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As noted in Section 7.1, the natural exponential component of the response of RL and RC circuits to step inputs diminishes as time passes. At t 1, the circuit reaches steady state and the response is made of the forced dc component only. Theoretically, it should take an in nite amount of time for RL or RC circuits to reach dc steady state. However, at t 5 , the transient component is reduced to 0.67 percent of its initial value. After passage of 10 time constants the transient component equals to 0.0045 percent of its initial value, which is less than 5 in 100,000, at which time for all practical purposes we may assume the steady state has been reached. At the dc steady state of RLC circuits, assuming no sustained oscillations exist in the circuit, all currents and voltages in the circuit are constants. When the voltage across a capacitor is constant, the current through it is zero. All capacitors, therefore, appear as open circuits in the dc steady state. Similarly, when the current through an inductor is constant, the voltage across it is zero. All inductors therefore appear as short circuits in the dc steady state. The circuit will be reduced to a dc-resistive case from which voltages across capacitors and currents through inductors can be easily found, as all the currents and voltages are constants and the analysis involves no di erential equations. The dc steady-state behavior presented in the preceding paragraph is valid for circuits containing any number of inductors, capacitors, and dc sources.

Fig. 7-13 (a) With a; a 0 open, id 0; hence, vgs 0 and vTh 0. After a driving-point source vaa0 is connected to terminals a; a 0 to drive current ia into terminal a, KVL gives vaa 0 vgs ia rds RD 1

7. An angle formed by two chords intersecting inside a circle is measured by one-half the sum of the intercepted arcs.

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EXAMPLE 7.7 Find the steady-state values of iL , vC1 , and vC2 in the circuit of Fig. 7-13(a). When the steady state is reached, the circuit will be as shown in Fig. 7-13(b). The inductor current and capacitor voltages are obtained by applying KCL at nodes A and B in Fig. 7-13(b). Thus, Node A: Node B: vA vA vB vA 18 vB 3 3 6 6 vB vB vA vB 18 vA 0 12 6 6 or or 2vA vB 0 4vA 5vB 36

Plan: When chord AD is drawn, /1 becomes an exterior angle of a triangle whose nonadjacent interior angles 1 1 are inscribed angles measured by 2 AC and 2 BD.

CHAP. 7]

Solving for vA and vB we nd vA 6 V and vB 12 V. By inspection of Fig. 7-13(b), we have iL 2 mA, vC1 8 V, and vC2 6 V. EXAMPLE 7.8 Find i and v in the circuit of Fig. 7-14. At t 0, the voltage across the capacitor is zero. Its nal value is obtained from dc analysis to be 2 V. The time constant of the circuit of Fig. 7-14, as derived in Example 7.6, is 0.034 s. Therefore, v 2 1 e 1000t=34 u t i C dv 9 10 2 10 1000t=34 e u t dt 34

PROOF:

6 3

But vgs vaa 0 , which can be substituted into (1) to give RTh vaa 0 r R ds D ia 1 1 2

Reasons 1. A straight line may be drawn between two points. 2. The measure of an exterior angle of a triangle equals the sum of the measures of the nonadjacent interior angles. 3. An angle inscribed in a circle is measured by one-half its intercepted arc. 4. Substitution Postulate

A sudden switching of a source or a jump in its magnitude can translate into sudden jumps in voltages or currents in a circuit. A jump in the capacitor voltage requires an impulse current. Similarly, a jump in the inductor current requires an impulse voltage. If no such impulses can be present, the capacitor voltages and the inductor currents remain continuous. Therefore, the post-switching conditions of L and C can be derived from their pre-switching conditions.

With vTh 0, insertion of RTh in place of the network to the right of a; a 0 in Fig. 7-13(a) leads directly to Fig. 7-13(b). (b) Applying KVL to the left of b; b 0 in Fig. 7-13(a) with b; b 0 open, while noting that vi vgs , yields vTh vi vgs 1 vi 3 Deactivating (shorting) vi , connecting a driving-point source vbb 0 to terminals b; b 0 to drive current ib into terminal b, noting that vgs ib RS , and applying KVL around the outer loop of Fig. 7-13(a) yield vbb 0 ib rds RS vgs ib rds 1 RS The Thevenin impedance follows from (4) as RTh vbb 0 rds 1 RS ib 5 4

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